The present invention relates in general to communication systems and components, and is particularly directed to a wireline voltage measurement circuit architecture, that is configured to generate a single ended output voltage that is very precisely proportional to the differential voltage across the tip and ring leads of a telephone wireline pair, at very low power consumption, making the voltage measurement circuit readily suited for incorporation into a subscriber line interface circuit (SLIC).
Various equipments employed by telecommunication service providers employ what are known as subscriber line interface circuits or xe2x80x98SLICxe2x80x99s, which interface (transmit and receive) communication signals with tip and ring leads of a (copper) wireline pair, to which a (remote) piece of subscriber equipment is connected. Not only is the wireline pair used to transport AC signals (e.g., voice and/or ringing), as well as substantial DC voltages, but its length can be expected to vary from installation to installation, and may be relatively long (e.g., on the order of multiple miles).
For optimized signal transmission and reception, the SLIC is designed to compensate for attenuation characteristics of the line. Because these attenuation characteristics strongly depend upon the length of the line, measuring the differential voltage across its tip and ring leads is usually performed to obtain an indication of line length. However, as this differential line voltage may be quite large, conventional loop voltage measurement circuits cannot be readily incorporated into present day, low voltage SLIC architectures, which are designed to be interfaced with a variety of telecommunication circuits including those providing digital codec functionality. This interface capability requires that the SLIC employ a transmission channel that conforms with a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low power consumption, low noise, filtering, and ease of impedance matching programmability.
As will be described, the present invention provides a new and improved loop voltage measurement circuit architecture, that is configured to produce a single ended output voltage, which is very precisely proportional to the differential voltage across the tip and ring leads of a telephone wireline pair. In so doing, the present invention consumes very little power and is designed to conform with the above referenced constraints of present day SLICs.
For this purpose, respective tip and ring leads of a telecommunication wireline pair of interest are coupled to a tip-ring voltage detector comprised of a transistor-configured tip-ring sensing (full wave) rectifier circuit containing complementary bipolar transistor pairs. Such rectifying arrangement enables proper operation regardless of the relative voltage polarity of the tip and ring terminals. The complementary transistor pairs of the rectifier circuit are intercoupled through a relatively high valued tip-ring voltage sensing resistor (on the order of one megohm), and have a collector-emitter output path coupled to a rectified detection current node. This detection current node supplies a current containing a composite of two voltage-representative components to a differential current extraction circuit. The first voltage-representative current component is representative of the differential tip-ring voltage (which is desired). The second voltage-representative current component is associated with the internal characteristics (base-emitter voltage drops of complementary transistors) of the tip-ring voltage detector (which constitutes an undesired offset).
The differential current extraction circuit serves to separate the second current component from the composite current. Each of the second current component and the composite current is then appropriately scaled, so that when differentially recombined, the scaled version of the second voltage-representative current component (which is associated with the internal characteristics of the tip-ring voltage detector) is canceled from the composite current, leaving only the first component representative of the differential tip-ring voltage.
For this purpose, the differential current extraction circuit contains a pair of current mirror circuits, one of which is a three port current mirror and generates a first current component that is fractionally proportional to the sum of the differential tip-ring voltage, plus the base-emitter voltage drops of the complementary pair of transistors of the tip-ring sense rectifier circuit. The other current mirror circuit is a two port current mirror that generates a second current component that is fractionally proportional to only the base-emitter voltage drops of the complementary pair of transistors of the tip-ring sense rectifier circuit.
One current mirror output port of the three-port current mirror is coupled to a single ended tip-ring voltage measurement node, to which a ground-referenced, voltage-dropping, output-scaling resistor is coupled. This output-scaling resistor has a resistance value that is a prescribed fraction of the value of the tip-ring sense resistor. A second current mirror output port of the three-port current mirror is coupled to an auxiliary voltage reference circuit, that is comprised of a pair of series-connected, complementary transistors that are coupled across a relatively large valued scaling resistor (which may have a value on the order of half that of the tip-ring sensing resistor).
The geometries (emitter areas) of the transistors of the auxiliary voltage reference are such that they operate at the same current densities as the transistor pairs of the tip-ring sensing rectifier. As a result, the output voltage produced by the auxiliary voltage reference is representative of only the base-emitter voltage drops of one of the complementary pairs of transistors of the rectifier. Therefore, the resultant current flowing through the scaling resistor, across which the voltage output of the auxiliary voltage reference is impressed, is representative of only the base-emitter voltage drops of a complementary pair of transistors of the rectifier.
By appropriately scaling and differentially combining this current with the current mirrored at the second port of the three-port current mirror (which is representative of the composite of the differential tip-ring voltage, plus the base-emitter voltage drops of a complementary pair of transistors of the rectifier), a resultant current representative of only the differential tip-ring voltage is obtained.
For this purpose, the current through the scaling resistor of the auxiliary voltage reference is coupled through a level shift transistor to a first (input) port of a two-port current mirror. A second (current mirror) port of the two port current mirror outputs a mirrored and attenuated current (which is representative of only the base-emitter voltage drops of a complementary pair of transistors of the rectifier) to the single ended tip-ring voltage measurement node. The scaling factor of this current is defined so as to have the same magnitude as the base-emitter voltage drop representative component of the mirrored current at the second (current mirror) port of the three-port current mirror, which is also coupled to the single ended tip-ring voltage measurement node.
The summing of the two mirrored and scaled currents at the single ended tip-ring voltage measurement node results in the base-emitter voltage drop components canceling one another, so as to produce a net output current through the voltage-dropping output-scaling resistor that is representative of only the differential tip-ring voltage, as desired.